Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Positive Edge
Polarity
Inverting, Non-Inverting
Mounting Type
Surface Mount
Package Type
DHVQFN
Pin Count
14
Set/Reset
Yes
Number of Elements per Chip
2
Maximum Propagation Delay Time @ Maximum CL
15 ns@ 1.2 V
Dimensions
3.1 x 2.6 x 0.95mm
Maximum Operating Supply Voltage
3.6 V
Minimum Operating Temperature
-40 °C
Height
0.95mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+125 °C
Length
3.1mm
Width
2.6mm
Minimum Operating Supply Voltage
1.2 V
Country of Origin
Thailand
Product details
74LVC Family Flip-Flops & Latches, Nexperia
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
SR 11.60
SR 0.58 Each (In a Pack of 20) (ex VAT)
SR 13.34
SR 0.667 Each (In a Pack of 20) (inc. VAT)
20
SR 11.60
SR 0.58 Each (In a Pack of 20) (ex VAT)
SR 13.34
SR 0.667 Each (In a Pack of 20) (inc. VAT)
Stock information temporarily unavailable. please contact rs@ae.com.sa for more details.
20
Stock information temporarily unavailable. please contact rs@ae.com.sa for more details.
Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Positive Edge
Polarity
Inverting, Non-Inverting
Mounting Type
Surface Mount
Package Type
DHVQFN
Pin Count
14
Set/Reset
Yes
Number of Elements per Chip
2
Maximum Propagation Delay Time @ Maximum CL
15 ns@ 1.2 V
Dimensions
3.1 x 2.6 x 0.95mm
Maximum Operating Supply Voltage
3.6 V
Minimum Operating Temperature
-40 °C
Height
0.95mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+125 °C
Length
3.1mm
Width
2.6mm
Minimum Operating Supply Voltage
1.2 V
Country of Origin
Thailand
Product details
74LVC Family Flip-Flops & Latches, Nexperia
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS