Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number of Channels
2
Schmitt Trigger Input
Yes
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
6
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
5.4 ns @ 3.3 V
Maximum Operating Supply Voltage
5.5 V
Dimensions
2.9 x 1.6 x 1.15mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+85 °C
Length
2.9mm
Height
1.15mm
Width
1.6mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC2G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
SR 937.50
SR 3.75 Each (On a Reel of 250) (ex VAT)
SR 1,078.12
SR 4.312 Each (On a Reel of 250) (inc. VAT)
250
SR 937.50
SR 3.75 Each (On a Reel of 250) (ex VAT)
SR 1,078.12
SR 4.312 Each (On a Reel of 250) (inc. VAT)
Stock information temporarily unavailable. please contact rs@ae.com.sa for more details.
250
Stock information temporarily unavailable. please contact rs@ae.com.sa for more details.
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number of Channels
2
Schmitt Trigger Input
Yes
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
6
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
5.4 ns @ 3.3 V
Maximum Operating Supply Voltage
5.5 V
Dimensions
2.9 x 1.6 x 1.15mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+85 °C
Length
2.9mm
Height
1.15mm
Width
1.6mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC2G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS


