Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
NOR
Mounting Type
Surface Mount
Number Of Elements
1
Number of Inputs per Gate
3
Schmitt Trigger Input
No
Package Type
SOT-23
Pin Count
6
Logic Family
LVC
Input Type
Differential
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-4mA
Maximum Propagation Delay Time @ Maximum CL
20.5 ns @ 50 pF
Minimum Operating Supply Voltage
1.65 V
Maximum Low Level Output Current
32mA
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Output Type
Single Ended
Length
3.05mm
Height
1.3mm
Width
1.75mm
Dimensions
3.05 x 1.75 x 1.3mm
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
Stock information temporarily unavailable.
SR 10.20
SR 0.51 Each (In a Pack of 20) (ex VAT)
SR 11.73
SR 0.586 Each (In a Pack of 20) (inc. VAT)
Standard
20
SR 10.20
SR 0.51 Each (In a Pack of 20) (ex VAT)
SR 11.73
SR 0.586 Each (In a Pack of 20) (inc. VAT)
Stock information temporarily unavailable.
Standard
20
Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
NOR
Mounting Type
Surface Mount
Number Of Elements
1
Number of Inputs per Gate
3
Schmitt Trigger Input
No
Package Type
SOT-23
Pin Count
6
Logic Family
LVC
Input Type
Differential
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-4mA
Maximum Propagation Delay Time @ Maximum CL
20.5 ns @ 50 pF
Minimum Operating Supply Voltage
1.65 V
Maximum Low Level Output Current
32mA
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Output Type
Single Ended
Length
3.05mm
Height
1.3mm
Width
1.75mm
Dimensions
3.05 x 1.75 x 1.3mm
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22


