Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Product Type
Buffer
Logic Function
Buffer
Number of Channels
1
Schmitt Trigger Input
Yes
Input Type
Single Ended
Mount Type
Surface
Output Type
Single Ended
Polarity
Non-Inverting
Minimum Supply Voltage
1.65V
Package Type
SOT-553
Maximum Supply Voltage
5.5V
Pin Count
5
Minimum Operating Temperature
-40°C
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Operating Temperature
85°C
Standards/Approvals
No
Series
SN74LVC1G17
Height
0.55mm
Length
1.7mm
Automotive Standard
No
Supply Current
-50mA
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
Stock information temporarily unavailable.
SR 19.80
SR 0.99 Each (In a Pack of 20) (ex VAT)
SR 22.77
SR 1.138 Each (In a Pack of 20) (inc. VAT)
Standard
20
SR 19.80
SR 0.99 Each (In a Pack of 20) (ex VAT)
SR 22.77
SR 1.138 Each (In a Pack of 20) (inc. VAT)
Stock information temporarily unavailable.
Standard
20
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Product Type
Buffer
Logic Function
Buffer
Number of Channels
1
Schmitt Trigger Input
Yes
Input Type
Single Ended
Mount Type
Surface
Output Type
Single Ended
Polarity
Non-Inverting
Minimum Supply Voltage
1.65V
Package Type
SOT-553
Maximum Supply Voltage
5.5V
Pin Count
5
Minimum Operating Temperature
-40°C
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Operating Temperature
85°C
Standards/Approvals
No
Series
SN74LVC1G17
Height
0.55mm
Length
1.7mm
Automotive Standard
No
Supply Current
-50mA
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22


