Technical Document
Specifications
Brand
Texas InstrumentsProduct Type
Flip Flop IC
Logic Family
LVC
Input Type
Single Ended
Output Type
Differential
Polarity
Non-Inverting, Inverting
Mount Type
Surface Mount
Package Type
SOIC
Minimum Supply Voltage
1.65V
Pin Count
16
Maximum Supply Voltage
3.6V
Flip-Flop Type
JK Type
Minimum Operating Temperature
-40°C
Trigger Type
Negative Edge
Maximum Operating Temperature
85°C
Number of Elements per Chip
2
Length
9.9mm
Height
1.58mm
Series
74LVC
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
Stock information temporarily unavailable.
P.O.A.
Each (In a Pack of 10) (ex VAT)
10
P.O.A.
Each (In a Pack of 10) (ex VAT)
Stock information temporarily unavailable.
10
Technical Document
Specifications
Brand
Texas InstrumentsProduct Type
Flip Flop IC
Logic Family
LVC
Input Type
Single Ended
Output Type
Differential
Polarity
Non-Inverting, Inverting
Mount Type
Surface Mount
Package Type
SOIC
Minimum Supply Voltage
1.65V
Pin Count
16
Maximum Supply Voltage
3.6V
Flip-Flop Type
JK Type
Minimum Operating Temperature
-40°C
Trigger Type
Negative Edge
Maximum Operating Temperature
85°C
Number of Elements per Chip
2
Length
9.9mm
Height
1.58mm
Series
74LVC
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22


