Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVT
Logic Function
Bus Transceiver
Number of Elements per Chip
1
Number of Channels per Chip
8
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
20
Input Level
LVTTL
Output Level
LVTTL
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
64mA
Maximum Propagation Delay Time @ Maximum CL
2.3 ns @ 3.3 V
Height
1.15mm
Width
4.4mm
Minimum Operating Temperature
-40 °C
Dimensions
6.5 x 4.4 x 1.15mm
Minimum Operating Supply Voltage
2.7 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
6.5mm
Maximum Operating Supply Voltage
3.6 V
Product details
74LVT Family, Texas Instruments
Low-Voltage BiCMOS logic
Operating Voltage: 2.7 to 3.6
Compatibility: Input LVTTL/TTL, Output LVTTL
74LVT Family
SR 5,360.00
SR 2.68 Each (On a Reel of 2000) (ex VAT)
SR 6,164.00
SR 3.082 Each (On a Reel of 2000) (inc. VAT)
2000
SR 5,360.00
SR 2.68 Each (On a Reel of 2000) (ex VAT)
SR 6,164.00
SR 3.082 Each (On a Reel of 2000) (inc. VAT)
Stock information temporarily unavailable. please contact rs@ae.com.sa for more details.
2000
Stock information temporarily unavailable. please contact rs@ae.com.sa for more details.
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVT
Logic Function
Bus Transceiver
Number of Elements per Chip
1
Number of Channels per Chip
8
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
20
Input Level
LVTTL
Output Level
LVTTL
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
64mA
Maximum Propagation Delay Time @ Maximum CL
2.3 ns @ 3.3 V
Height
1.15mm
Width
4.4mm
Minimum Operating Temperature
-40 °C
Dimensions
6.5 x 4.4 x 1.15mm
Minimum Operating Supply Voltage
2.7 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
6.5mm
Maximum Operating Supply Voltage
3.6 V
Product details
74LVT Family, Texas Instruments
Low-Voltage BiCMOS logic
Operating Voltage: 2.7 to 3.6
Compatibility: Input LVTTL/TTL, Output LVTTL